PLC Memory elements


#1

Memory elements are used to store intermediate values. Memory function are achieved using flags ( bit memory locations) and system memory. Specified bit memory can be set or reset using a set coil. A latch in ladder logic uses one instruction to latch and a second instruction to unlatch, as shown in Figure 1.9. The output with an S inside will turn the output D on when the input A becomes true. D will stay on even if A turns off. Output D will turn off if input B becomes true and output with a R inside becomes True.

PLC%20Memory%20elements

Both set coil and reset coil can be combined in one box as shown in Figure 1.10. Following
instructions are to be followed while writing a program for memory function

  • Setting up a memory location
  • Resetting up a memory location

The memory address locations vary from manufacturer to manufacturer. For sake of simplicity we shall use M1, M2 … to represent memory. Number of bit memories available in PLC for memory are 1024, 2048 8192 and more. If the power flows either momentarily or continuously to the set coil, the specified memory address is set to signal state 1.

If power flows momentarily or continuously to the reset coil , the corresponding memory address is reset to signal state 0. If there is no power in the set input or reset input, the memory address remains unaffected. The output of the memory function can be accessed through either NO or NC program element.

Set and reset functions are combined in one memory box as shown in Figure 1.10.

They can be further classified into two categories

a) Memory box with set priority b) Memory box with reset priority

The functions of a memory box are similar to the memory coils. In the memory box with set priority, the associated memory address is set when signal state 1 appears simultaneously at both the set and reset inputs. In the memory box with reset priority, the associated memory address is reset when signal state 1 appears simultaneously at both reset and set inputs. This concept is similar to Dominant ON and Dominant OFF functions of electrical latching circuits.